A 4GHz direct digital frequency synthesizer utilizing a nonlinear sine-weighted DAC in 90nm CMOS
Hong Chang Yeoh, Kwang‐Hyun Baek · 2008
A nonlinear sine-weighted Digital-to-Analog Converter (DAC) can significantly reduces the power consumption and the complexity of Direct Digital Frequency Synthesizers (DDFSs). With the sine conversion implemented in the DAC, the Phase-to-Amplitude Mapping (PAM) stage can be totally eliminated, thus drastically reduces the latency and increases the speed of the DDFS as the PAM stage is usually the speed bottleneck of a DDFS design. Utilizing quarter wave mapping technique, the simulated results of the DDFS with a 7-bit sine approximation using a modified binary-to-thermometer decoder, current switch and driver achieve a maximum Spurious Free Dynamic Range (SFDR) of 53 dBc at low synthesized output and better than 44 dBc across the whole Nyquist range when clocked at 4GHz. Designed and simulated in 90nm CMOS, this monolithic DDFS has 6 clock cycle latency and consumes only 462mW when operating at 4Gsample/s.