A design of a fast and area efficient multi-input Muller C-element
Tzyh-Yung Wuu, Sarma B. K. Vrudhula · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1993
A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection in self-timed circuits. An n-input Muller C-element design which uses the multilevel logic design technique and has a symmetric format for any integer n >or=2 is presented. In comparison with series-parallel MOS structure implementations and C-element tree implementations, the present design has fewer restrictions in terms of n, less path delay, less delay variance from inputs to output, and less area consumption. Experimental validation based on an industrial standard cell library is presented.>