Roundoff error reduction in state-space digital filters of cascade type
Toshinori Yoshikawa, Tetsuya Kato · Electronics and Communications in Japan (Part III Fundamental Electronic Science) · 1997
Some problems with realization of digital filters are caused by roundoff errors due to the word-length restriction. Effects of these errors can be reduced if the processing range for large signals is chosen so as to avoid overflow. For filters built according to the state-space expressions, one uses scaling which is aimed at the state variables. However, since no constraints apply to the output value computation, it results in a non-efficient use of the dynamic range and an increase in the relative error. On the other hand, in a cascade-type structure, the coefficient matrix of the entire system is computed from the coefficient matrices of all sections. Such a computing procedure leads to an increased number of multipliers and, therefore, increased roundoff error. To solve this problem, the authors have proposed a method based on scaling aimed at the output value computation which enables efficient use of the dynamic range. In addition, the realization was based on the original coefficients of the sections in a cascade structure, which allowed reducing the number of multipliers. The proposed computing procedure offers significant time savings. This realization method was demonstrated by introducing auxiliary state variables. In particular, for the cascade structure, significant reduction of the roundoff error was achieved. As a numerical example, we computed the roundoff error for a low-pass elliptic filter. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 3, 80(10): 87–96, 1997