Delay estimation VLSI circuits from a high-level view
Mahadevamurty Nemani, Farid N. Najm · 1998
Estimation of the delay of a Boolean function from its functional description is an important step towards design exploration at the register transfer level (RTL). This paper addresses the problem of estimating the delay of certain optimal multi-level implementations of combinational circuits, given only their functional description. The proposed delay model uses a new complexity measure called the delay measure to estimate the delay. It has an advantage that it can be used to predict both, the minimum delay (associated with an optimum delay implementation) and the maximum delay (associated with an optimum area implementation) of a Boolean function without actually resorting to logic synthesis. The model is empirical and results demonstrating its feasibility and utility are presented. 1. Introduction Rapid increase in the design complexity and reduction in design time have resulted in a need for CAD tools that can help make important design decisions early in the design process. To do...