Adaptive testing - Cost reduction through test pattern sampling
M. Grady, Bradley Pepper, Joshua Patch, Michael Degregorio, Phil Nigh · 2013
In this paper, we will present two different applications of “test pattern sampling” for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.