Using Logic BIST to Test the PIC Block in FPGA
Aiqin Bian · ECS Transactions · 2013
This paper presents using the Logic BIST (Build-in Self-test) implementation on the PIC (Program IO Cell) block test for FPGA. Self-test is achieved by utilizing the test resource available in the FPGA. Test vectors are generated and compared internally, which makes the PIC test package independent and compatible to sort test because this implementation requires only minimum number of IO pins. Therefore it makes the PIC block test more effectively by eliminating the need to consider the different packaging of the device, which dramatically lowers the manufacture test development cost and time. The experiment shows very promising results. The amount of the test patterns is reduced by 77%. The test development cycle time is reduced by 48% compared to the traditional test method. Though the number of pattern is reduced, the test coverage is not compromised which is guaranteed by taking all PIC test configurations into account. This implementation was illustrated on PIC block in this paper. But it is applicable to testing other FPGA typical blocks, such as EBR, DSP and PLC using the proposed logic BIST method.