Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture
Takashi Shimizu, Masayuki Nakajima, Masahiro Kainaga · IEICE Transactions on Electronics · 2006
This paper describes the design and evaluation of a massively parallel processor base on Matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves 40GOPS of 16-bit fixed-point additions at 200MHz clock frequency and 250 mW power dissipation. In addition, 1 M-bit SRAM for data registers and 2,048 2-bit processing elements connected by a flexible switching network are integrated in 3.1 mm 2 in 90 nm low-power CMOS technology. The energy-efficient Matrix architecture supports 2,048-way parallel operations and the programmable functions required for multimedia SoCs.