Novel self-test methods to reduce on-chip memory requirements and improved test coverage
Prakash Narayanan, Satish Ravichandran, Balaji Ramayanam · 2014
Self-Test is one of the most important requirements for automotive class of devices. The different automotive devices have different fault coverage requirements (90%-95%) for the cores as per different Automotive Safety Integrity Level (e.g. ASIL-B, ASIL-C, etc.). Logic self-test is achieved by way of either random patterns or deterministic automatic test pattern generation (ATPG). Random patterns are generated by using Logic Built-in Self-Test (LBIST), which have their own limitations in terms of achievable coverage. Deterministic ATPG has been used to bridge the coverage gap but have additional requirements in terms of on-chip memory to store the generated pattern sets. In this work we will show how deterministic ATPG can be used in a novel way to bridge the coverage gap while reducing the on-chip memory requirements.