Hardware/Software Partitioning and Scheduling Algorithm Based on FPGA
Lanying Li, Longjuan Chen · 2014
For low power consumption of system structure in embedded heterogeneous multi-core processor, decompose the hardware/software partitioning into task partitioning and low power scheduling in two stages. The algorithm of reducing power consumption is adopted at each stage, and finally optimal algorithm of two stages will be integrated in order to achieve the system goal of maximum reduction of the power consumption.