A parallel decimal adder with carry correction during binary accumulation
Kuan Jen Lin, Ju Lin Shih, Tsz Hao Lin, Yu Mei Wang · 2012
Dedicated hardware for decimal floating point arithmetic is becoming a necessity in commercial and financial applications which demand high speed decimal computation. Multi-operand decimal addition is the core of other arithmetic operations, such as multiplication and division. In this paper, we propose a new parallel adder which uses binary CSAs to accumulate BCD-8421 input operands and perform carry corrections during the accumulation. The correction means that certain values must be added to the preliminary sum to ensure that proper BCD results are produced. The proposed approach attempts to minimize the number of additional operands required for the corrections. The synthesis result is obtained using Synopsys Design Compiler Topographical Technology with TSMC 0.18um library.