Design and chip implementation of an instruction scheduling free ubiquitous processor
Masa-aki Fukase, Ryosuke Murakami, Tomoaki Sato · Asia and South Pacific Design Automation Conference · 2010
Instruction scheduling is a crucial issue for cutting edge VLSI processors that exploit parallelism to solve the tradeoff between clock speed and power dissipation. A double scheme for multiple pipelines merges their scalar units into a multifunctional unit (MFU) and makes the MFU wave-pipeline. Parallelizing a resultant pipeline achieves instruction scheduling free due to multifunctionality. Applied such approach to the latest design of a ubiquitous processor, HCgorilla, this is implemented by using 0.18-µm CMOS standard cell chip.