A bit‐sliced design for a programmable digital filter
Yung‐Chang Chen, Nan‐Chang Lin · Journal of the Chinese Institute of Engineers · 1983
A 14‐span programmable low‐pass FIR digital filter is implemented with a decimation structure. With the aid of bitsliced technique, the tedious data flow that results from sharing unified arithmetic circuits can be operated in real‐time mode, and the sampling rate is up to 102.4 KHz.