A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications
Meng‐Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan‐Hua Chu, Wen-Chin Wu, H. Yamauchi · 2010
A 90 nm 256 Kb NAND-ROM using read-1 noise elimination and read-0 sensing-margin-expanding schemes is functional at 0.29 V and 3 MHz with 100% code-coverage and 5% area overhead. This work reduces the delay-per-BL-length, energy-per-bit at VDDmin, and VDDmin-delay-product by 3000×, 4× and 3700×, respectively, compared to previous low-voltage ROMs.