27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI
Matthew Weiner, Milovan Blagojević, Sergey Skotnikov, Andreas Peter Burg, Philippe Flatresse, Borivoje Nikolić · 2014
Low-density parity-check (LDPC) codes in modern wireless communications are rate- and throughput-scalable, and despite their complexity, decoding them requires low power consumption. The IEEE 802.11ad standard for Gb/s wireless LANs in the 60GHz band requires an implementation of an LDPC encoder/decoder with throughputs of 1.5, 3, and 6Gb/s, with code rates of 1/2, 5/8, 3/4 and 13/16 [1]. Previous implementations of decoders for these throughputs and levels of reconfiguration have power consumptions on the order of the rest of the baseband processing [2,3]. This paper presents a fully compatible IEEE 802.11ad LDPC decoder in 28nm ultra-thin body and BOX fully-depleted SOI (UTBB FDSOI) technology with a power consumption that is a small fraction of the total baseband power. To achieve this, the decoder introduces an approximate marginalization technique and a simplified reconfiguration method. Forward body biasing of FDSOI technology allows for minimum energy consumption across all decoding modes.