Configurable architecture for memory BIST
Atieh Lotfi, Parisa Sha'afi Kabiri, Zainalabedin Navabi · 2011
The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed.