7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip
Hyunjin Kim, Jeong-Don Lim, Jangwoo Lee, Daehoon Na, Joonho Shin, Chaehoon Kim, Seungwoo Yu, Ji-Yeon Shin, Seon‐Kyoo Lee, Devraj Rajagopal, Sang‐Tae Kim, Kyeong-Tae Kang, Jeong-Joon Park, Yong-Jin Kwon, Min‐Jae Lee, Sung‐Hoon Kim, Seunghoon Shin, Hyung-Gon Kim, Jin-Tae Kim, Ki-Sung Kim · 2015
NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and high-throughput performance. In recent years, a SATA interface supporting only up to 600MB/S throughput has hindered the accelerating performance growth of SSDs due to the host bandwidth limit. A PCI Express (PCIe) has emerged to close the limit because it can deliver 1GB/s throughput per lane and can be scaled to multi-lane to improve bandwidth [1]. Accordingly, the SSD performance bottleneck has moved from the host interface to the NAND flash interface. In a memory system, a die-stacking technology in a NAND flash multi-chip package (MCP) effectively increases capacity and throughput performance in terms of PCB complexities and power consumption compared to a method increasing the number of channels. However, the multi-drop bus topology on NAND interfaces severely affects I/O speed degradations due to channel reflections and inter-symbol interference (ISI) resulting from large capacitive loadings [2]. The undeniable paradox between larger storage capacity and higher I/O bandwidth has become a key challenge to reach enterprise-class SSDs. To overcome this issue, this paper presents a frequency-boosting interface chip (F-Chip) to boost I/O speeds while meeting capacity requirements. A 2Tb NAND flash MCP with 1GB/s toggle DDR interface is accomplished by incorporating the F-Chip into the NAND MCP including a 16-die stacked 128Gb NAND flash [3].