Very low power consumption Viterbi decoder LSICemployingthe SST (scarce state transition) scheme for multimedia mobile communications
Kazuhiko Seki, Shun-ichi Kubota, Masaru Mizoguchi, Shuzo Kato · Electronics Letters · 1994
A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8 µm CMOS masterslice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600 µW at a supply voltage of 1 V when the data rate is 1152 kbit/s and the bit error rate is less than 10-3 This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting.