Improvements in Parallel Chimera Grid Assembly
Nathan C. Prewitt, Davy M. Belk, Wei Shyy · AIAA Journal · 2002
Parallel implementation and performance assessment of the grid assembly function in a chimera grid approach, realized by the Beggar code, are presented. A mixed programming model is used combining message passing with shared-memory programming constructs using standard POSIX calls. The POSIX calls are used to store large, common data structures in shared memory. The associated reduction in the total memory requirements allows more processors to be used. The effective utilization of this increased processor count is based on improvements in load balancing because of a finer decomposition of the work associated with the grid assembly function. Parallel efficiency is demonstrated using a three-store, ripple release, trajectory calculation.