Hardware efficient FIR filter implementation using subfilters for digital receivers
A. P. Vinod, Edmund M-K Lai, A. Benjamin Premkumar, Chiew Tong Lau · 2003
Digital filters employed in the intermediate frequency (IF) block of wide-band receivers present a hardware design challenge. The computational complexity of fixed-point filters is dominated by the number of adders used in the implementation of the multipliers. It has been shown that using common subexpression elimination to exploit redundancy across the canonic signed digit (CSD) coefficients results in filters with minimum number of adders. In this paper, we propose a method to efficiently implement linear phase finite impulse response (LPFIR) filters using subfilters obtained from the filter coefficients represented in binary. We present an algorithm that extracts the most suitable subfilters from the coefficient pairs and obtains the unmatched terms of coefficients from these subfilters by simple shift operations. Design examples show that filters implemented using proposed method require fewer adders than conventional CSD based common subexpression elimination methods.