A C-based RTL design verification methodology for complex microprocessor
Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Young Choi, Wooseung Yang, Hun-Seung Oh, In‐Cheol Park, Chong-Min Kyung · 1997
As the complexity of high-performance microprocessor increases,functional verification becomes more and more difficultand RTL simulation emerges as the bottleneck of thedesign cycle.In this paper, we suggest C language-based designand verification methodology to enhance the simulationspeed instead of the conventional HDL-based methodologies.RTL C model (StreC) describes the cycle-based behaviors ofsynchronous circuits and is followed by model refining andoptimization using LifeTime Analyzer (LTA) and Cleaner.The simulation speed of cycle-based C model makes it possibleto test the RTL design with the "real-world" applicationprograms in the order-of-magnitude faster speed thanthe commercial event-driven simulators.Using the proposedfunctional verification methodology, HK486, an intel 80486 - compatiblemicroprocessor was successfully designed and verified.