Approaches to design of circuits for low-power computation
Priyadarsan Patra · 1996
Great advances in technology over the last few decades have led to a convergence of computing and communications, and to quantum leaps in the capabilities of the resulting information hardware. Until recently, these improvements have been largely based on ever decreasing sizes of the features that can be fabricated on a silicon substrate. However, further improvements are now faced with a new limiting factor--power consumption. Both energy supply and its dissipation pose serious problems to realizing ultra-dense, peta-ops machines of the future. Decreasing power dissipation in both static and active operations of electronic systems depends on synergistic advancements in the development of materials technology, device technology, circuit architecture, and overall power management strategies. One architectural approach to power conservation in digital systems involves selectively clocking portions of a circuit, so that they consume power only when they are being used. While this technique is currently employed in ad hoc ways in modern synchronous processors, delay-insensitive (DI) circuits provide a natural way to achieve these benefits automatically. This dissertation develops a theory of completeness and minimality of sets of primitives with respect to a large class of DI circuits. We design many useful DI modules giving their efficient and novel decompositions to minimize the number of internal switching events--which translate to lower energy consumption--and/or increase circuit throughput. Switch-level designs of some DI primitives are demonstrated. Furthermore, we develop a notion of dynamic, delay-insensitive data transmission and present various protocols to reduce energy usage in such communications. In this dissertation, we study synchronous as well as self-timed circuits under the general rubric of computation. We introduce a theory of conservative and delay-insensitive computing as the basis for a design approach to ultra low-power computation in circuits where destruction of information--which fundamentally involves energy dissipation--is minimized. Moreover, we argue that these DI circuits will likely be competitive in size, if not distinctly better, when implemented on an event-based technology such as the Charge Coupled Device, or Superconducting Single Flux Quantum devices. Finally, we investigate area-efficient design techniques for clocked, adiabatic circuits and identify some sources of energy dissipation that are shown to be avoidable.