A synthesis method of systolic algorithms for nested loop programs
Daisuke Miura, Hirotomo Aso, Yasuyoshi Inagaki · Systems and Computers in Japan · 1988
Abstract The development of VLSI technology makes possible the implementation of systolic algorithms as silicon chips are placed in many operational cells arranged in an array. This paper describes a synthesis method of systolic algorithms for problems whose solving procedures are described by a certain kind of nested loop program. A systolic algorithm is specified by a geometry of systolic array, function of processing cells, and timing of data streams flowing among the cells. The synthesis method provides a systematic function of cells and timing of data streams for a given geometry of systolic arrays so that computation procedures of a loop program are executed in parallel. The algorithm obtained is represented not by a heuristic expression, but by a procedure description language. The nested loop programs to be designed by the synthesis method include such matrix manipulations as multiplication, addition and LU decomposition, and also such basic operations in the relational algebra as selection, join, and sorting, all of which are demonstrated.