Multi-level EDT to Reduce Scan Channels in SoC Designs
Guoliang Li, Jun Qian, Peter Li, Greg Zuo · 2012
This paper presents a new multi-level EDT scheme to reduce scan channels of scan-based SoC designs. Multi-level EDT requires trivial modification on existing EDT scheme with two-pass encoding. Experimental results show that this scheme can reduce channel count by up to 30% without penalty of test coverage and pattern count.