FPGA implementation of full HD real-time depth estimation
Hejian Li, Ping An, Guowei Teng, Zhaoyang Zhang · 2014
Depth estimation is a common task in stereo vision system and usually requires a high computational effort. High resolution images offer more details compared to low resolution images and high resolution depth maps are necessary to provide a good image quality on autostereoscopic displays which deliver stereo content without the need for 3D glasses. In this paper, a FPGA architecture for depth estimation is proposed, that is capable of processing full HD content with processing speed of 125fps and a disparity search range of 240 pixels. The resulting architecture is efficient in terms of power consumption and overall performance improvement.