An 8-Core 64-Thread 64b Power-Efficient SPARC SoC
Umesh Gajanan Nawathe, Mohamad Sayed Hassan, Lynn Warriner, King Yen, Bharat Upputuri, David Greenhill, Ashok S. Kumar, Heechoul Park · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2007
The 8-core 64-thread 64b power-efficient 2nd-generation Niagara SPARC SoC has 4MB L2 cache with one times8 PCI-Express, two 10G Ethernet (XAUI), and 8 FBDIMM ports. The on-chip SerDes provide greater than 1Tb/s bandwidth. The 500M transistor chip with a die size of 342mm2is implemented in a 11M 65nm triple-VtCMOS process