Chip hierarchical design system (CHDS)
R. G. Bushroe, Shamik Dasgupta, Aykut Dengi, Paul Tepper Fisher, S. Grout, G. Ledenbach, N.S. Nagaraj, Robert Steele · 1997
Thispaperpresents the descrtption of the architecture of the Chip Hierarchical Design System (CHDS) and details on the requiredTiming Driven Physical Design capabilities that have been defined to satisfy the physical design needs for 0.234 technologies and beyond.These requirements are intended to solve the challenges including the Design Productivity Crisis identijed by semiconductor industry, the shi$ in the design paradigm where the timing of a physical design will be dominated by interconnect effects, and the need for an integrated physicar design system which still supports "plug-and-play" through the use of EDA standard languages, moak's, and inte$aces.