Symmetry in temporal logic model checking
Alice Ann Miller, Alastair F. Donaldson, Muffy Calder · ACM Computing Surveys · 2006
Temporal logic model checking involves checking the state-space of a model of a system to determine whether errors can occur in the system. Often this involves checking symmetrically equivalent areas of the state-space. The use of symmetry reduction to increase the efficiency of model checking has inspired a wealth of activity in the area of model checking research. We provide a survey of the associated literature.