A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing
Anh Tuan Do, Shoushun Chen, Zhi Hui Kong, Kiat Seng Yeo · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2012
Content addressable memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line (ML) comparison, CAM is power-hungry. Thus, robust, high-speed and low-powerMLsense amplifiers are highly sought-after in CAM designs. In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. Furthermore, we propose an effective gated-power technique to reduce the peak and average power consumption and enhance the robustness of the design against process variations. A feedback loop is employed to auto-turn off the power supply to the comparison elements and hence reduce the average power consumption by 64%. The proposed design can work at a supply voltage down to 0.5 V.