Network processor architecture for flexible buffer management in very high speed line interfaces
Hideyuki Shimonishi, Tutomu Murase · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2001
In this paper, the proposed architecture is described and the results obtained when evaluating it in a typical application program for traffic handling are reported. It is shown that the architecture enables Weighted Round Robin packet scheduling at 4.1 Gbps line speed, in addition to 10 Gbps IP packet forwarding and 2.4 Gbps IP/ATM multi-layer switching.