A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA
Sudhakar Maddi, M. Srinivas · 2007
This paper presents an improved version of unified Montgomery multiplier architecture to reduce the critical path delay leading to higher data throughput. It is known that the critical path delay due to four-to-two carry save adders (CSAs), which have two levels of carry-save logic, is predominant in determining the overall performance of the CSA based multipliers. In this paper, authors improve the multiplier efficiency by replacing four-to-two CSA with new one level area-efficient sum-carry logic. While conventional four-to-two CSA has a delay of four .xor. gates, the proposed sum-carry logic has a delay of only two .xor. gates. Not only does this result in reduced critical path delay but also results in reduced area compared to previous multiplier architectures. Also it can compute n-bit multiplication in n+2 clock cycles in both fields GF(p) and GF(2n). Further, the critical path delay is independent of input operand precision.