Clock-efficient and maintainable implementation of complex state machines in VHDL
W. Zabołotny · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2006
This paper presents a nonstandard approach to describe the complex state machines in VHDL to obtain both good readability of the code and efficient operation. This new approach, called "variable driven flow control in sequential process" allows to avoid loss of clock cycles when complex decisions are to be taken, and simultaneously allows to keep the structure of the code clear and easy to maintain. A simple example has been presented, showing the idea and practical implementation of the proposed method. The code produced by the presented method is synthesizable, and the obtained parameters of resulting FPGA implementation (both speed and occupancy) are good.