A verification technique for gated clock
Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto Luigi Sangiovanni-Vincentelli · 1993
We present a new model for circuits which have memory elements using conditional clocking, This is termed as the “gated” clock problem. Conventionally most of the recent efforts in timing analysis focus on memory elements controlled by clock signals only, We describe a simple restriction on the conditional signale which makes automatic verification easy. An algorithm to solve the timing verification problem for the case of restricted circuits based on previous approaches is given.