FASTRUN - A High Performance Computing Device for Molecular Mechanics Using a Pipeline Architecture
D. Gerd Dimmler, Richard Fine, Cyrus Levinthal · IEEE Transactions on Nuclear Science · 1986
A deep, synchronous pipeline architecture has been selected for a computing device with a power of 500 Million floating point operations per second (MFlops). The device calculates the forces and energy due to pair-wise interactions of many objects in a system. Considerations relating to application specific high-performance computer architectures are addressed. In addition, topics specifically relating to very deep, synchronous unidirectional pipelines are discussed. A key element of the device, a quadratic interpolator based on a lookup table, has been developed and tested. Five of these interpolators with a total computing power of 280 Mflops will be employed in the device.