A single chip motion JPEG codec LSI
Shigeyuki Okada, Yoshio Matsuda, T. Watanabe, Katsuhiko Kondo · IEEE Transactions on Consumer Electronics · 1997
We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640 pixels/spl times/480 lines) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI can control compression ratio control technique to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer to enable high-speed signal processing without the use of high-speed image memory. The JPEG codec core is small (40000 gates) and power consumption is low (220 mW), making it well suited to a wide range of image processing applications in consumer products.