GaAs 800-mb/s serial communications chip set
Kelvin G. Hickman · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1990
A high-speed communications chip set based on a 1500-gate structured cell gate array, designed specifically for interprocessor communications in multiprocessor environments has been developed. Needing a minimum of support logic, these three chips provide all link functions, including parallel/serial and serial/parallel conversion, data encoding/decoding, idle/quiet line detection, data clock phase recovery, and link error indicators. The link clock rate is 1 GHz, supporting a data rate of 800 megabit/second.