A FPGA based real-time post-processing architecture for active stereo vision
Seung‐Min Choi, Jiho Chang, Dae Hwan Hwang · 2014
This paper presents a post-processing architecture for high quality depth map in active stereo vision. The proposed architecture consists of five sub-blocks in cascade manner, which are consistency check, hole filling, variance check, weighted median filter, and joint bilateral filter. The novel design which is implemented on a single FPGA achieves 60 frames per second for 1280×720 stereo images with 256 disparity range.