An implementation of capabilities on the PDP-11/45
Charles G. Hoch, J. C. Browne · ACM SIGOPS Operating Systems Review · 1980
This paper defines a capability implementation which uses the memory management hardware and the TRAP instruction of the higher members of the Digital Equipment Corporation PDP-11/XX (XX = 34, 45, 55, 70) to create a capability architecture processor. No modifications to hardware are necessary. The architecture created has a strong similarity to that of the Plessey 250. An operating system based on this architecture could provide a basis for implementation of highly reliable and secure software systems on a common and inexpensive minicomputer.