A Large Scale, Flip-Flop RAM imitating a logic LSI for fast development of process technology
Masako Fujii, Koji Nii, Hiroshi Makino, S. Ohbayashi, Mitsuhiko Igarashi, T. Kawamura, Michio Yokota, Nobuhiro TSUDA, Tomoaki YOSHIZAWA, Toshikazu Tsutsui, N. Takeshita, Naofumi Murata, T. Tanaka, Toshiki Fujiwara, K. Asahina, M. Okada, Kendall Tom, Masahiko Takeuchi, Hirofumi Shinohara · 2007
We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.