A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions
Takashi Nakayama, H. Harigai, Shingo Kojima, Hiroya Kaneko, Hiroshi Igarashi, T. Toba, Y. Yamagami, Yoshiko Yano · IEEE Journal of Solid-State Circuits · 1989
An 80-bit floating-point coprocessor which implements 24 vector/matrix instructions and 22 mathematical functions is described. This processor can execute floating-point addition/rounding and pipelined multiplication concurrently, under the control of horizontal-type microinstructions. The SRT division method and CORDIC trigonometrical algorithm are used for a favorable cost/performance implementation. The performance of 6.7 MFLOPS in the vector-matrix multiplication at 20 MHz has been attained by the use of parallel operations. The vector/matrix instruction is about three times faster than conventional add and multiply instructions. The chip has been fabricated in 1.2- mu m double-metal layer CMOS process containing 433000 transistors on a 11.6*14.9-mm/sup 2/ die size.>