A 16K × 1 bit dynamic RAM
Peter J. Schroeder, RobertJ Proebsting · 1977
.4 16K x 1. BIT dynamic RAM capable of 130-ns access time has been developed using a two-level N-channel polysilicon gate process and a single transistor cell. Utilizing the standard 16-pin package configuration, seven address bits are multiplexed. All clocks and other inputs are TTI. compatible. Maximum user flexibility has been provided by incorporating ± 10% supplies, a nonlatehed tri-state data output controlled by CAS, a+ multiplex timing window, page mode capability, and RAS-only refresh