Optimization of memory utilization for partially parallel QC-LDPC decoder
Tsung-Che Wu, Yaowen Hu, Chang‐Ming Lee · 2010
Quasi-cyclic (QC) low-density parity-check (LDPC) codes have advantages over other types of LDPC codes due to their cyclic shifting property. In this paper, a partially parallel QC-LDPC decoder with efficient memory design is proposed. To improve the memory utilization, the structures of efficient chunk and predictor are realized. The efficient chunk can store parts of check-to-variable messages. This design can effectively reduce the memory requirement. Furthermore, the predictor verifies variable-to-check messages and updates efficient chunks instantly. With less check-to-variable messages and variable-to-check messages stored in the memory, this decoding architecture only deposits few messages in several efficient chunks, such that the cost of memory is less. Eventually, the proposed approach dramatically reduces memory requirement about 65% compared to the traditional method while maintaining the same low-cost.