An Advanced NAND-Structure Cell Technology for Reliable 3.3 V 64 Mb Electrically Erasable and Programmable Read Only Memories (EEPROMs)
S. Aritome, Ikuo Hatakeyama, Tetsuo Endoh, Tetsuya Yamaguchi, S. Shuto, Hirohisa Iizuka, Tooru Maruyama, Hiroshi K. WATANABE, Gertjan Hemink, Koji Sakui, Tomoharu Tanaka, M. Momodomi, R. Shirota · Japanese Journal of Applied Physics · 1994
An extremely small NAND-structure cell of 1.13 µm2 per bit, 80% of the smallest Flash memory cell reported so far [H. Kume et al.: IEEE Tech. Dig. IEDM (1992) p. 991], has been developed in 0.4 µm technology. The chip size of a 64 Mb NAND electrically erasable and programmable read only memory (EEPROM) using this cell is estimated to be 120 mm2, which is 60% that of a 64 Mb DRAM. In order to realize the small cell size, a 0.8 µm field isolation is used. A negative bias of -0.5 V to the P-well of the memory cell is applied during writing. In addition, a bit-by-bit intelligent writing technology allows a 3.3 V data sensing scheme which can suppress read disturb to 1/1000 in comparison with the conventional 5 V scheme. As a result, it is expected that with this technology, 106 write and erase cycles can be achieved and that the tunnel oxide can be scaled down from 10 nm to 8 nm.