High-speed hardware architectures for authenticated encryption mode GCM
Akashi Satoh · 2006
We propose various high-speed hardware architectures for GCM (Galois counter mode) in conjunction with various AES (advanced encryption standard) hardware macros, and clarify the trade-offs between speed and hardware resources. The designs were evaluated by using a 0.13-mum CMOS standard cell library. The highest throughput of 42.7 Gbps with 297 Kgates was obtained from a sequential GCM architecture with a full-pipelined AES circuit where a 128-bit data block is processed on every clock, and the smallest size of 73 Kgates with 6.4 Gbps was achieved with pipelined-loop architecture. All of our architectures support key sizes of 128, 192, and 256 bits, while only one previous approach does. Even with variable-length key support, all of our designs showed higher performance than conventional designs