Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks
Daewoong Kim, Kilhyung Cha, Soonwoo Choi, Soo‐Ik Chae · 2009
A multi-core platform for high-performance video applications is proposed that contains multiple RISC clusters. Each cluster, which contains up to four cores and exploits thread-level parallelism, is allocated for a function block and connected to other clusters through two communication networks: one for control transfer and the other for data transfer. As an example, several mapping results of the H.264/AVC high profile 720 p decoder to the proposed platform are presented. According to the experimental results, we found that this platform is suitable for implementing a multi-standard video codec.