Parameter and UVM, making a layered testbench powerful
Geng Lei Zhong, Jian Long Zhou, Bei Xia · 2013
Parameterized design is highly increasing the flexibility and reusability of the integrated circuit. Meanwhile, it requires additional verification effort over verifying an un-parameterized design. Consequently, flexible verification strategies must be developed to ensure the verification process of parameterized design. UVM was built on the principle of cooperation between EDA vendors and customers. It is based on SystemVerilog classes, and proven to be a powerful OOP technique with highly reusability. In this case, how to develop a parameterized UVM testbench is a major concern. This paper demonstrates a method that has proven useful within a layered UVM testbench. First, this paper discusses how to create parameterized UVM. Then, it focuses on parameterized interconnection and interoperable (Layer-Layer Communication and DUT-TB Communication).At last, to illustrate the method, a parameterized UVM env based on the method is developed. It is proven useful in different kinds of scenarios.