Memory interfacing and instruction specification for reconfigurable processors
Jeffrey A. Jacob, Paul Chow · 1999
As custom computing machines evolve, it is clear that a major bottleneck is the slow interconnection architecture between the logic and memory.This paper describes the architecture of a custom computing machine that overcomes the interconnection bottleneck by closely integrating a fixed-logic processor, a reconfigurable logic array, and memory into a single chip, called OneChip-98.The OneChip-system has a seamless programming model that enables the programmer to easily specify instructions without additional complex instruction decoding hardware.As well, there is a simple scheme for mapping instructions to the corresponding programming bits.To allow the processor and the reconfigurable array to execute concurrently, the programming model utilizes a novel memory-consistency scheme implemented in the hardware.To evaluate the feasibility of the OneChip-architecture, a 32-bit MIPS-like processor and several performance enhancement applications were mapped to the Transmogrifier-2 field programmable system.For two typical applications, the 2-dimensional discrete cosine transform and the 64-tap FIR filter, we were capable of achieving a performance speedup of over 30 times that of a stand-alone state-of-the-art processor.1.