High efficiency and low power multi-rate LDPC decoder design for CMMB
Xiaobo Jiang, Hongyuan Li · 2011
High efficiency and low power LDPC decoder for CMMB that supports two rates has been designed in the paper. Layered min-sum algorithm and memory compression technology are adopted to reduce the usage of memory; backup memory method is applied to solve memory read/write conflict existing in CMMB LDPC code at a low cost of memory resource; operational unit multiplexing which can process 1/2 bit rate and 3/4 bit rate simultaneously is used so that the resource consumption of operational unit is reduced. The LDPC decoder designed in this paper is synthesized in the SMC0.18um process. The synthesized result has indicated that the area of designed CMMB LDPC decoder is 7.6mm2 and its power consumption is 132.8mW.