Proposal for ultra-high speed scheduling architecture
Kazuto Nishimura, Atsushi Kitada, Hiroshi Tomonaga, Tsutomu Noguchi · 2013
It has recently become more difficult for packet processing switches, which have very high speed interface cards, to achieve rich Quality of Service (QoS) functions because such high-speed switches have insufficient packet processing times. In particular, the scheduler/shaper is one of the greatest hindrances to increasing the speed of processing because it selects a suitable queue based on complex algorithms (e.g., weighted round robin (WRR) or strict priority (SP)) in a limited time. One solution that mitigates this scheduling/shaping speed problem is burst packet processing. However, burst packet processing has several side effects. We analyze these side effects and propose a scheduling architecture that minimizes them. We also show the effectiveness of our proposed architecture based on simulation results.