(V)HDL-based verification of heterogeneous synchronous/asynchronous systems
Hans Eveking · European Design Automation Conference · 1994
The modelling and veri cation of two types of heterogeneous systems is discussed: (i) systems consisting of synchronous subsystems with di erent clocks, and (ii) systems which are composed of synchronous and asynchronous subsystems. Concurrent behaviour is represented in VHDL by means of additional input signals, i.e., \concurrency is additional inputs plus fairness. State space exploration techniques for mixed synchronous/asynchronous systems are presented.