Low-Latency Implementation of Coordinate Conversion in Virtex II pro FPGA
Grzegorz Jabłoński, Konrad Przygoda · 2007
The paper presents a low-latency implementation of Cartesian-polar coordinate conversion in a Virtex II pro FPGA. The accuracy and resource consumption of the module is comparable to the one obtained with the Xilinx CORDIC IP Core, but the latency has been reduced to 65%. The application of the conversion module to the cavity detuning computation in low-level radio frequency control system for a FLASH accelerator has been also presented.